1. Field of the Invention
The present invention relates to a semiconductor device in which an SOI (Silicon On Insulator) substrate is used as a semiconductor substrate and a diode is formed in the surface silicon layer of the semiconductor substrate, and a method of fabricating the semiconductor device.
2. Description of the Related Art
In an SOI substrate, a plurality of surface silicon layers, which are isolated by a buried oxide film, are formed like islands on a silicon substrate.
It has been tried that semiconductor components such as transistors and diodes are formed in the surface silicon layers, using the SOI substrates, therewith a PN junction region of a semiconductor component can be completely isolated from other components, so it is expected that various problems caused by incomplete isolation can be solved.
As an example of the above semiconductor device, a semiconductor device in which a diode is formed in a surface silicon layer of an SOI substrate will be introduced hereinafter. FIG. 29 is a schematic sectional view showing the principal structure of the semiconductor device.
In the semiconductor device shown in FIG. 29, used is an SOI substrate 1 in which a plurality of surface silicon layers 3 isolated by a buried oxide film 19 are provided like islands (only one surface silicon layer is shown in the drawing) on a silicon substrate 17 which is a supporting substrate, and a diode 2 is formed in the surface silicon layer 3.
In the diode 2, a PN junction region with a p region 5 and an n region 7 is provided in the surface silicon layer 3, and a heavily doped p region 13 is provided at a portion on the surface side in the p region 5, and a heavily doped n region 9 is provided at a portion on the surface side in the n region 7 respectively.
A silicon oxide film 21 is provided to cover all the surface of the heavily doped n region 9, the n region 7, the p region 5, and the heavily doped p region 13, and furthermore an insulating film 23 is provided to cover the silicon oxide film 21.
Contact holes 12 and 14 are respectively formed in the silicon oxide film 21 and the insulating film 23 at locations corresponding to the heavily doped n region 9 and the heavily doped p region 13. From the outside through the contact holes 12 and 14, formed are metal plates 11 and 15 which electrically contact the heavily doped n region 9 and the heavily doped p region 13 respectively.
Next, a method of fabricating the semiconductor device will be explained with reference to FIG. 30 through FIG. 41. Each of the drawings is a schematic sectional view showing the fabricating process of the semiconductor device shown in FIG. 29 in due order.
First, the aforesaid SOI substrate 1 is prepared, and p impurities are ion-implanted into the surface silicon layer 3 which is isolated by the buried oxide film 19 to be provided like an island on a silicon substrate 17. Then, the implanted p impurities are diffused by heat-treating to form the p region 5 as shown in FIG. 30. Thereafter, the surface of the p region 5 is oxidized to form the silicon oxide film 21 on the whole surface of the surface silicon layer 3.
Sequentially, a photoresist is formed on the whole surface of the silicon oxide film 21 by spin coating and then is patterned, by exposing and developing with a predetermined photomask, so as to form a photoresist 22 in such a manner as to open a region where the n region is formed as shown in FIG. 31.
Then, using the photoresist 22 as an ion implantation barrier film, n impurities are ion-implanted into the p region 5 of the surface silicon layer 3 through the silicon oxide film 21. Thereafter, when the photoresist 22 is removed and then the implanted n impurities are diffused by heat-treating, the n region 7 is formed as shown in FIG. 32.
Next, a photoresist is formed again on the whole surface of the silicon oxide film 21 by spin coating and then is patterned, by exposing and developing with a predetermined photomask, so that a photoresist 24 is formed in such a manner as to open a region where the heavily doped n region is formed as shown in FIG. 33.
Then, using the photoresist 24 as an ion implantation barrier film, n impurities are ion-implanted into the n region 7 of the surface silicon layer 3 through the silicon oxide film 21, so that the heavily doped n region 9 shown in FIG. 34 is formed. Thereafter, the photoresist 24 shown in FIG. 33 is removed.
Thereafter, a photoresist is formed again on the whole surface of the silicon oxide film 21 by spin coating and then is patterned, by exposing and developing with a predetermined photomask, so that a photoresist 26 is formed in such a manner as to open a region where the heavily doped p region is formed as shown in FIG. 35.
Then, using the photoresist 26 as an ion implantation barrier film, p impurities are ion-implanted into the p region 5 of the surface silicon layer 3 through the silicon oxide film 21 to form the heavily doped p region 13 shown in FIG. 36. Thereafter, the photoresist 26 shown in FIG. 35 is removed.
Sequentially, as shown in FIG. 37, the insulating film 23 is formed to cover the whole surface of the silicon oxide film 21.
Thereafter, by heat-treating in a nitrogen atmosphere, the heavily doped n region 9 and the heavily doped p region 13 are electrically activated. It is noted that the heat-treatment in the nitrogen atmosphere serves as a reflowing treatment in which the uneven surface of the insulating film 23 is made flat.
Next, as shown in FIG. 38, a photoresist 28 is formed on the whole surface of the SOI substrate 1 by spin coating and then is patterned, by exposing and developing with a predetermined photomask, in such a manner as to provide openings 28a and 28b at locations over the insulating film 23 and the silicon oxide film 21 where the contact holes are formed.
Then using the photoresist 28 as a mask, the insulating film 23 and the silicon oxide film 21 under the openings 28a and 28b are completely removed by etching to form the contact holes 12 and 14 shown in FIG. 39. Thereafter, the photoresist 28 is removed.
Sequentially, as shown in FIG. 40, a film 30 made of metal plate material with aluminium is formed on the whole surface of the SOI substrate 1 and in the contact holes 12 and 14.
Next, a photoresist is formed on the whole surface of the film 30 of the metal plate material by spin coating and then is patterned, by exposing and developing with a predetermined photomask, in such a manner as to leave a photoresist 32 only on the regions where metal plates will be formed as shown in FIG. 41.
Then, using the photoresist 32 as a mask, the unmasked portion of the film 30 of the metal plate material is completely removed by etching to form the metal plates 11 and 15 shown in FIG. 29. The metal plate 11 electrically contacts to the heavily doped n region 9 and similarly, the metal plate 15 electrically contacts to the heavily doped p region 13, respectively. Thereafter, the photoresist 32 is removed, resulting in the completion of the semiconductor device in which the diode 2 shown in FIG. 29 is formed on the SOI substrate.
In the semiconductor device shown in FIG. 29 fabricated as above, the p region and the n region are formed in the surface silicon layer of the SOI substrate by an ion-implantation and a heat-treatment. The impurity profile, where the p region or the n region is formed in the silicon layer by the ion-implantation and the heat-treatment, generally shows a curved line indicating that the impurity concentration is the highest in the vicinity of the surface of the silicon layer.
Accordingly, in the diode 2 in the semiconductor device shown in FIG. 29, a surface junction region 3a located in the vicinity of the surface of the surface silicon layer 3 is the highest in impurity concentration in the PN junction surface which is formed with the p region 5 and the n region 7.
Generally, the PN junction, the higher the impurity concentration is, hard to spread the depletion layer and the junction breakdown voltage becomes low. Therefore, in the case of the diode 2 shown in FIG. 29, a breakdown occurs earliest at the surface junction region 3a in the surface silicon layer 3. When the breakdown occurs, carriers appear avalanche like in the depletion layer, and the carriers which have gained high energy there jump over an energy barrier to flow into the silicon oxide film 21. In the case of the diode 2 shown in FIG. 29, electrons are injected from the n region 7 in the vicinity of the surface junction region 3a into the silicon oxide film 21.
The carriers that are once injected into the silicon oxide film 21 are confined in the silicon oxide film 21, and are hard to be released therefrom to the outside. Therefore, electrons are captured in the silicon oxide film 21, which influences formation of a negative electric field in the direction from the surface of the n region 7 toward the silicon oxide film 21. With the influence of the electric field, the surface of the n region 7 changes to a state where electrons are ejected and are difficult to stay therein, so that the carrier concentration decreases in the vicinity of the surface of the n region 7. Thereby, the value of resistance per unit area in the surface portion (sheet resistance) becomes high and the current during forward bias becomes small.
If the PN junction is reverse-biased in a state where electrons are captured in the silicon oxide film 21, electrons are released from the surface of the n region 7 under the electric field which is formed with the electrons, resulting in a state where the depletion layer is more likely to spread out. Accordingly, the junction breakdown voltage comes to be high.
As described above, the diode has characteristics that once carriers are injected into the silicon oxide film, the current becomes small during forward bias and the junction breakdown voltage becomes high during reverse bias. The diode of the semiconductor device shown in FIG. 29 has a disadvantage that the device characteristics are varied by captured electrons in the silicon oxide film 21 when a breakdown occurs.
In other words, the diode which has been examined as the semiconductor device using the above SOI substrate has disadvantages that a breakdown occurs in the vicinity of the interface between the surface silicon layer 3 and the silicon oxide film 21, and the device characteristics are varied by the influence of carriers which flow into the silicon oxide film 21 with the breakdown, so that not only sufficient performance can not be obtained but also, at worst, a misoperation is caused in a circuit of which high accuracy is required.